(1) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a method for fabricating a semiconductor device having interconnections buried in trenches.
(2) Description of the Related Art
Aluminum (Al) based alloy is now widely used as the interconnection material of semiconductor devices, because Al has a relatively low resistivity and fine interconnections can be formed by dry etching. However, as semiconductor devices are scaled down and the interconnection width is reduced, there arise problems such as degraded performance of semiconductor devices due to high resistance of interconnections or breakage in interconnections due to electromigration and stressmigration.
In contrast, copper (Cu) has a lower resistivity, higher melting point, and higher electromigration and stressmigration resistance than Al. Therefore, low resistance interconnections and long lifetime can be expected so that Cu is the leading candidate to replace Al as the interconnection material. However, as compared to Al, the disadvantages associated with Cu are difficulties of dry etching Cu and forming fine interconnections. To solve this problem, a trench burying Cu interconnection technology has been proposed. This trench burying interconnection technology aims to form high planar and low resistance multilevel Cu interconnections, without using a dry etch of Cu.
FIGS. 1A to 1D are cross sectional views sequentially illustrating a process flow of a method of forming a trench burying Cu interconnection, this technology being described in "Technical Digest of Symposium on VLSI Technology", by J. S. H. Cho et al., pp. 39-40 (1991).
As shown in FIG. 1A, an interconnection trench 209a is formed in a silicon oxide film 202b formed on a silicon substrate 201, and thereafter a TiW film 210a is formed. Next, as shown in FIG. 1B, photoresist (PR) is coated and etched back to leave a PR mask 212 and a TiW film 210a in the interconnection trench 209a.
As shown in FIG. 1C, after the PR mask 212 is removed, silicon nitride is deposited and etched back to form a spacer of a silicon nitride film 213 on the side wall of the interconnection trench. Then, as shown in FIG. 1D, a tungsten (W) film 210b, a Cu film 211a, and a W film 210c are sequentially formed in the interconnection trench to thereby form a trench burying interconnection having Cu as its main conductive layer.
Also in the above cited paper "Technical Digest of Symposium on VLSI Technology", by J. S. H. Cho et al., p. 39 (1991), two contact structures to a diffusion layer are described. FIGS. 2A and 2B are cross sectional views of the contact structures.
In the structure shown in FIG. 2A, a diffusion layer 203a is formed in the region surrounded by a field oxide film 202a, a contact hole 205a is formed in a silicon oxide film 204 formed on the diffusion layer 203a, and a W film 210b, a Cu film 211a, and a W film 210c are sequentially formed in the contact hole. In the other structure shown in FIG. 2B, after a W film 210b is formed on a diffusion layer 203a, a silicon oxide film 204 is deposited and a contact hole 205a is formed therein. Thereafter, a Cu film 211a and a W film 210c are sequentially formed in the contact hole.
Multilevel trench burying Cu interconnections have been proposed by S. Lakshminarayanan et al. in "Proceedings of VLSI Multilevel Interconnection Conference (VMIC)", at pp. 49-55 (1994). FIGS. 3A-3H are cross sectional views and plan views illustrating a sequence of processes.
As shown in FIG. 3A, a lower level interconnection trench 209b is formed in a silicon oxide film 202b formed on a silicon substrate 201. Next, as shown in FIG. 3B, after a titanium (Ti) film 210e is formed, Cu is deposited by Chemical Vapor Deposition (CVD) to fill the lower level interconnection trench 209b with a Cu film 211b. Next, as shown in FIG. 3C, the Cu film 211b and Ti film 210e over the silicon oxide film 202b are partially removed by Chemical Mechanical Polishing (CMP) so as to form a lower level interconnection 203b in the lower level interconnection trench 209b, the lower level interconnection 203b being constituted by the Ti film 210e and Cu film 211b. A silicon oxide film 204 is deposited over the lower level interconnection 203b and, thereafter, an interconnection trench 209a is formed in the silicon oxide film 204.
With the above processes, the positional relationship between the lower level interconnection 203b and interconnection trench 209a becomes as shown in FIG. 3D assuming that there is no alignment error or size error (size error between an actual pattern and its mask pattern). As shown in FIG. 3E, a through-hole 205b is formed in the silicon oxide film 204 in the area of the interconnection trench 209a, reaching the surface of the lower level interconnection 203b. After the above processes, the positional relationship among the lower level interconnection 203b, interconnection trench 209a, and through-hole 205b becomes as shown in FIG. 3F. Next, as shown in FIG. 3G, after a Ti film 210d is formed, a Cu film 211a is deposited by CVD.
As shown in FIG. 3H, the Ti film 210d and Cu film 211a over the silicon oxide film 204 are partially removed by CMP to form both a Cu contact plug and a trench burying Cu interconnection at the same time on the lower level interconnection 203b.
Forming a contact plug or lower level interconnection through CMP is called a Damascene process. Forming a contact plug and trench burying interconnection by a single CMP process at the same time is called a dual Damascene process.
Although not shown in drawings, forming multilevel trench burying Cu interconnections by the dual Damascene process is reported in "Proceedings of VLSI Multilevel Interconnection Conference (VMIC)", by D. C. Edelstein et al., at pp. 511-513 (1993). In this paper, trench burying Cu interconnections of three or more layers are realized by using polyimide as an insulating film, in the manner similar to S. Lakshminarayanan et al.
A trench burying Cu interconnection proposed by J. S. H. Cho et al. is formed by leaving a TiW film only in the interconnection trench by an etchback process using photoresist as an etching mask, by forming a side wall silicon nitride film, and thereafter by sequentially forming a W film, a Cu film, and a W film in the interconnection trench. Accordingly, this method requires a number of interconnection forming processes as compared to the Damascene process, resulting in an increased manufacturing cost. Furthermore, a W film is formed by a selective W-CVD process which requires high process precision so that a high production yield is difficult.
The two contact structures proposed in the same paper by J. S. H. Cho et al. are also associated with the severe problems that a manufacturing cost is increased and a high production yield is difficult.
As compared to the method given by J. S. H. Cho et al., the Damascene method used by S. Lakshminarayanan et al. is simple and has less processes, and easy to control processes because stable processes are used. However, with the dual Damascene method for multilevel interconnections by which a plug for a contact hole (inclusive of a through-hole) and a trench burying interconnection are formed at the same time, the contact hole is formed after the interconnection trench is formed so that photoresist for the contact hole cannot be coated uniformly because of steps of the interconnection trench.
A change in the film thickness of photoresist does not have a significant affect much if there is a large margin between a contact hole and an interconnection trench or if a large pattern is used. However, for a margin-less contact (contact hole, diffusion layer, and interconnection of the same size) or a fine pattern, it is difficult to satisfy the requirements of high alignment precision. In addition, a pattern size error caused by exposure becomes large and pattern deformation easily occurs.
FIGS. 4A to 4F are cross sectional views and plan views illustrating the process flow corresponding to the second conventional technique in which a margin-less contact is used, while comparing the cases with and without an alignment error.
As shown in FIG. 4A, if there is neither a size error nor an alignment error when a through-hole 205b is formed after an interconnection trench 209a is formed in a silicon oxide film 204 on a lower level interconnection 203b, then the positional relationship among the lower level interconnection 203b, through-hole 205b, and interconnection trench 209a becomes ideal as shown in FIG. 4B. Accordingly, after a Ti film 210d and a Cu film 211a are deposited and subjected to CMP, a trench burying Cu interconnection of two layers is formed as being margin-less as shown in FIG. 4C.
It is generally difficult to perform a patterning process without any alignment and size error. The reasons of the occurrence of a size error may be as follows: 1) If a thickness of a photoresist film is uneven, a smaller pattern is formed at the thick area and a larger pattern is formed at a thin area; 2) If different widths of patterns are used, a wider pattern is made even more wider whereas a narrower pattern is made even more narrower; and 3) If there is a distortion of an exposure lens, the pattern size is made different depending upon the position on a wafer.
As shown in FIG. 4D, assuming that there is an alignment error during an exposure process for forming a through-hole, the positional relationship among the lower level interconnection 203b, through-hole 205b, and interconnection trench 209a becomes as shown in FIG. 4E. In this case, even the silicon oxide film 202b at the side of the lower level interconnection 203b may be over-etched when the through-hole is opened. This over-etch degrades the shape of the through-hole and so a void is easily formed when a metal film is filled in the interconnection trench. Worse still, this over-etch may cause the through-hole to reach the substrate or lower level interconnection so that an electrical short occurs. This makes it impossible to attain a good electrical performance and high production yield. Similar problems also occur when there is a size error during the exposure process for a through-hole (contact hole), so that a good electrical performance and high production yield are impossible.